1. Field of the Invention
The present invention relates to the provision of a semiconductor chip scale package with through-vias which can be either isolated or electrically connected to a substrate. Moreover, the invention also relates to a method of producing a semiconductor chip scale package with through-vias which can be isolated or electrically connected to a substrate.
2. Discussion of the Prior Art
In the present state-of-the-art technology, semiconductor chip scale packages are installed in ever increasing numbers in diverse applications into portable devices, for example, such as cell phones, PDAs and cameras, among others. Generally, semiconductor chip scale packages for CMOS image sensors are adapted to be in electrical contact from the backside of a wafer in order to prevent any damage being encountered by a microlens, which is normally arranged on the frontside of the wafer. Provision is made for the presence of through-vias, which are employed in order to be able to facilitate the making of electrical contact with bond pads, generally also employing a dielectric in order to isolate the through-vias from the substrate. However, to an increasing extent, in various physical and commercial applications and installations, it is desirable to have some of the vias in electrical contact with the substrate. Thus, for instance, pursuant to specific example, a method which is employed in order to minimize electrical cross-talk in CMOS imager arrays resides in the utilization of an n-type silicon substrate; in effect, a doped silicon material, while forming the photodiode in a p-type epi layer. Hereby, the n-type silicon layer must be biased in order to capture deep photo-carriers, whereby it is necessary to provide for a contact thereof with a substrate. However, currently the technology does not permit for the formation of through-vias which are isolated from the substrate in some regions and which are electrically connected to the substrate in other regions.
At this time, the prior art is represented and described in connection with semiconductor chip scale packages in an article by Jürgen Leib and Michael Töpper, entitled “New Wafer-Level-Packaging Technology Using Silicon-Via-Contacts for Optical and Other Sensor Applications”; 2004 Electronic Components and Technology Conference of the IEEE; Pages 843-847. In that instance, although basic consideration is given to the provision of silicon via contacts, which are employed for optical and other sensor applications, there is no disclosure provided for having various though-vias electrically contacting a substrate or, alternatively, other vias being isolated from the substrate within the same semiconductor chip scale package.